Mail Index

• Thread Index

• [oc] Transfering data via I2C Master Core
  • From: "matija habek" <mhabek@net.hr>
• [oc] Clock frequency generator
  • From: cool_canguy@indiatimes.com
• [oc] Fwd: your software
  • From: "Ariadne Hunt" <a.huntmw@lycos.com>
• Re: [oc] SNR Calculation using CADENCE SpectreS tool
  • From: ghittori@ele.unipv.it
• [oc] LogiCore 1024 point FFT issue ?
  • From: "Saumil Merchant" <msaumil@hotmail.com>
• Re: [oc] Uart 16550 Wishbone to Avalon
  • From: "Robinluo\(Cytech FAE\)" <robinluo@cytecht.com>
• [oc] Uart 16550 Wishbone to Avalon
  • From: "Jared Francom" <jared@lnxi.com>
• [oc] programming xc95144 with Parallel cable IV
  • From: "Haytham Azmi" <haythamazmi@hotmail.com>
• RE: [oc] vhdl question
  • From: spyros_s@freemail.gr (spyros)
• Re: [oc] Re: code for usart
  • From: aarati_tina@yahoo.com
• Re: [oc] vhdl question
  • From: Atul Ware <baluware@yahoo.co.in>
• RE: [oc] numeric PIN or PAD number
  • From: "Jerrold Wen" <jwen@visualsonics.com>
• Odp: [oc] vhdl question
  • From: "Jerzy G" <furia1024@wp.pl>
• Re: [oc] vhdl question
  • From: "Henchinski" <kaliski@bezeqint.net>
• Re: [oc] vhdl question
  • From: spyros <spyros_s@freemail.gr>
• [oc] vhdl question
  • From: "Saumil Merchant" <msaumil@hotmail.com>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: "Jim Dempsey" <tapedisk@ameritech.net>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: "H. Peter Anvin" <hpa@zytor.com>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: Umair Farooq Siddiqi <ufarooq.geo@yahoo.com>
• RE: [oc] verilog CAN core implementation issues
  • From: "Igor Mohor\(opencores\)" <igorm@opencores.org>
• Re: [oc] interfacing 16Mhz and I Mhz clock registers
  • From: John Sheahan <jrsheahan@optushome.com.au>
• [oc] interfacing 16Mhz and I Mhz clock registers
  • From: Umair Farooq Siddiqi <ufarooq.geo@yahoo.com>
• Re: [oc] linux xilinx webpack programming
  • From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
• Re: [oc] linux xilinx webpack programming
  • From: amir_helzer@hotmail.com
• Re: [oc] VHDL PID Motor Controller
  • From: Michael.van.der.velden@philips.com
• [oc] help,TMAX question.
  • From: "Gengbo" <geng_bo@sh.t2-design.com>
• Re: [oc] Query abt Switch level modelling in Verilog
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] numeric PIN or PAD number
  • From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
• Re: [oc] Query abt Switch level modelling in Verilog
  • From: "R. Ramakrishna" <rayaprolu_rk@yahoo.com>
• [oc] numeric PIN or PAD number
  • From: paul <paulw@mmail.ath.cx>
• Re: [oc] constraints while programming in VHDL
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] constraints while programming in VHDL
  • From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
• Re: [oc] constraints while programming in VHDL
  • From: ritika_dua@yahoo.com
• Re: Re: [oc] 8-PSK
  • From: "henry_xb" <xxiaobin@263.net>
• Re: [oc] 8-PSK
  • From: "Haytham" <haythamazmi@hotmail.com>
• [oc] 8-PSK
  • From: liawkh@hotmail.com
• [oc] Swan cum-writer Cores esivunguvungwini
  • From: Shawn Saltzgaber <ablabius@ranmamail.com>
• Re: [oc] Query abt Switch level modelling in Verilog
  • From: John Sheahan <jrsheahan@optushome.com.au>
• [oc] =?GB2312?B?s6zWtdeqyMMtLbGxvqm498DgxvPStUhSo6jIy8Gm18rUtL6twO2jqcP7wrw=?=
  • From: =?GB2312?B?zuK2qw==?= <11@err.com>
• [oc] Query abt Switch level modelling in Verilog
  • From: "R. Ramakrishna" <rayaprolu_rk@yahoo.com>
• Re: [oc] The use of both edge of the clock.
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] The use of both edge of the clock.
  • From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
• Re: [oc] verilog CAN core implementation issues
  • From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
• [oc] The use of both edge of the clock.
  • From: <nico@seul.org>
• [oc] verilog CAN core implementation issues
  • From: anthonymarino@ieee.org
• RE: [oc] VHDL Help...
  • From: "Larsen, Henning Engelbrecht" <h.larsen@risoe.dk>
• [oc] OpenTech cdroms new release
  • From: Jamil Khatib <jamilkhatib75@yahoo.com>
• ReRe: [oc] MP3 Encoder?
  • From: otto otto <damc4@gmx.de>
• Re: [oc] MP3 Encoder?
  • From: hannakutty@yahoo.com
• Re: [oc] verilog coding standards document
  • From: "R. Ramakrishna" <rayaprolu_rk@yahoo.com>
• Re: [oc] verilog coding standards document
  • From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
• Re: [oc] verilog coding standards document
  • From: Marko Mlinar <markom@opencores.org>
• [oc] verilog coding standards document
  • From: "Ana Rita Matias (WITHUS)" <withus-a-matias@ptinovacao.pt>
• Re: [oc] [PATCH] UART receiver bugs
  • From: Jacob Gorban <jacobg@flextronics.co.il>
• [oc] [PATCH] UART receiver bugs
  • From: Scott Furman <sfurman@rosum.com>
• Re: [oc] Re: ip help
  • From: Shawn Tan <shawn.tan@aeste.net>
• [oc] Re: ip help
  • From: =?gb2312?B?1cXJvbjV?= <samchanghn@hotmail.com>
• Re: [oc] VHDL Help...
  • From: Jason Silcox <jsilcox@yahoo.com>
• Re: [oc] uart modem outputs
  • From: Jacob Gorban <jacobg@flextronics.co.il>
• RE: [oc] uart modem outputs
  • From: "Leo Jarillas" <leo.jarillas@eazix.com>
• Re: [oc] uart modem outputs
  • From: John Sheahan <jrsheahan@optushome.com.au>
• Re: [oc] TMS34010
  • From: Paul Cousoulis <paulcsouls@worldnet.att.net>
• [oc] uart modem outputs
  • From: "Leo Jarillas" <leo.jarillas@eazix.com>
• Re: [oc] core for FFT/IFFT (1024 point)for 802.11a protocol
  • From: rjrodrig@yahoo.com
• Re: [oc] TMS34010
  • From: Charles Lepple <charles@motioncontrol.org>
• [oc] TMS34010
  • From: Paul Cousoulis <paulcsouls@worldnet.att.net>
• Re: [oc] Patents and their applicability
  • From: alex patience <abpatience@australink.net>
• Re: [oc] or1200 compilation problem
  • From: "Damjan Lampret" <lampret@opencores.org>
• [oc] I thought that this might be interesting.
  • From: Lars Segerlund <lars.segerlund@comsys.se>
• [oc] or1200 compilation problem
  • From: paul <paulw@mmail.ath.cx>
• Re: [oc] DMA in ethernet
  • From: "Igor Mohor" <igorm@opencores.org>
• Re: [oc] Delay and latency ?
  • From: Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>
• Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
  • From: =?UTF-8?B?Sm9hY2hpbSBTdHLDtm1iZXJnc29u?=<Joachim.Strombergson@InformAsic.com>
• Re: [oc] Delay and latency ?
  • From: Marko Mlinar <markom@opencores.org>
• Re: [oc] wishbone performance
  • From: Marko Mlinar <markom@opencores.org>
• [oc] DMA in ethernet
  • From: ksvenkat@tenet.res.in
• [oc] If anyone has a free AMBA AHB to wishbone or AHB master or slave
  • From: j1234f@excite.com
• Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
  • From: Tom Hawkins <tom1@launchbird.com>
• Re: [oc] Newbie question - matricies and vectors for physics
  • From: Tom Hawkins <tom1@launchbird.com>
• Re: [oc] Delay and latency ?
  • From: John Dalton <john.dalton@bigfoot.com>
• Re: [oc] 8255 PPI VHDL CODE
  • From: "Robinluo\(Cytech FAE\)" <robinluo@cytecht.com>
• [oc] 8255 PPI VHDL CODE
  • From: anmolsethy@rediff.com