RE: [oc] VHDL Help...

["Larsen, Henning Engelbrecht" <h.larsen@risoe.dk>]

Yes, synthesizers dont like math.real. Ive run into the exact same problem when trying to write code which is easy to maintain and which adapt well to varying data sizes. I made a package with this small code snippet. Its debatable what ceil_log2(0) should be. Ive set it to 1, but in mathematical terms its undefined, so chose what you find fits your purpose

  function ceil_log2 (a : integer) RETURN integer is
  begin
    assert a>=0 report "Illegal argument to ceil_log2" severity failure; 
	-- ...some synthesizers dont like asserts either, so comment this out or enclose in conditionals   
    if (a < 0) then 
	return 0;             -- 0 or whatever to signal that you are out of bounds
    elsif (a = 0) then return 1;-- hmm. maybe should we boom out with an error here also
    else
      for j in 1 to a loop -- but this is good..
        if (2**j >= a) then
          return j;
        end if;
      end loop;
    end if;
  end ceil_log2;

regards
henning larsen
Risoe National Laboratory
Denmark


> -----Original Message-----
> From: Jason Silcox [mailto:jsilcox@yahoo.com]
> Sent: 9. juni 2003 00:55
> To: cores@opencores.org
> Subject: Re: [oc] VHDL Help...
> 
> 
> 
> I've tried to do this exact "trick"...
> 
> When you try to synthesize this entity it will fail...
> 
> IEEE.MATH_REAL is not implemented in most synthesis
> tools and thus the CEIL and LOG2 functions will not
> be found...
> 
> I figured the synthesis tool would evaluated the
> expression first and when it realized it was a constant
> it wouldn't need a synthesizable model of the MATH_REAL
> functions, but that was not the case...
> 
> If anyone does create a synthesizable version of this,
> please e-mail it too me...
> 
> Thanks,
> ---
> Jason Silcox
> 
> --- Shehryar Shaheen <shehryar.shaheen@ul.ie> wrote:
> > Try this
> > 
> > LIBRARY IEEE;
> > USE IEEE.STD_LOGIC_1164.ALL;
> > USE IEEE.STD_LOGIC_ARITH.ALL;
> > USE IEEE.STD_LOGIC_UNSIGNED.ALL;
> > USE IEEE.MATH_REAL.ALL;                   <-- Add this package
> > 
> > ENTITY mux IS
> > GENERIC( size_data : integer := 8 );
> > PORT(
> >            data : IN STD_LOGIC_VECTOR(size_data-1 downto 0);
> >            sel  : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(
> > size_data)))) downto 0);   <-- Put this line in place
> >            result : OUT STD_LOGIC
> >         );
> > END mux;
> > 
> > This should work if your compiler is VHDL93 compliant
> > in case you are using modelsim complie it with these switches
> > 
> 
> 
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