Re: [oc] interfacing 16Mhz and I Mhz clock registers

[John Sheahan <jrsheahan@optushome.com.au>]

On Fri, 2003-06-20 at 13:02, Jim Dempsey wrote:
> 
> ----- Original Message -----
> From: "John Sheahan" <jrsheahan@optushome.com.au>
> To: <cores@opencores.org>
> Sent: Thursday, June 19, 2003 5:45 PM
> Subject: Re: [oc] interfacing 16Mhz and I Mhz clock registers
> 
> 
> > On Fri, 2003-06-20 at 02:34, Umair Farooq Siddiqi wrote:
> > > I can adjust skew between two clocks, at present there is no skew
> between them, 1 Mhz Clock can be considered as 16Mhz clock divided by 16.
> > >
> > > Thanks
> >
> > (its early and my coffee is not working yet. please think thru these
> > points)
> >
> > Sounds like the clocks are synchronous then - which simplifies things a
> > lot. Otherwise memories and junk may be required.
> >
> > If the 16M and the 1M are exactly in phase, there is no issue - you can
> > connect them directly q -> D
> 
> Not so quickly. If the leading edge of the 1M and the leading edge of one of
> 16 of the 16M's then your statement is true for only that one out of the 16
> clock ticks. Note, depending on how things are wired up you may be
> restricted to using that one (in phase) tick for intercommunication. Also,
> nothing has been said about the dwell time that the clock pulse is held high
> (and/or low). You may need to handshake on the slower clock when moving data
> between domains.
> 

Sorry - I don't understand your points here.
I don't care about duty cycle  for edge triggered D flops.
I don't care about the other 15 clock edges as there is no destination
clock.
Yes - there is unstated assumption that the data rate through this is
limited to 16bits/1MHz. And a matching assumption that something else 
ensures the data presented in the 16MHz domain is meaningful every 16th
tick. .   
There is also an unstated assumption that any skew on the data is small
compared to the 16MHz period.

john 




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