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[oc] Query abt Switch level modelling in Verilog

To: cores@opencores.org
Subject: [oc] Query abt Switch level modelling in Verilog
From: "R. Ramakrishna" <rayaprolu_rk@yahoo.com>
Date: Fri, 13 Jun 2003 22:52:23 -0700 (PDT)
In-Reply-To: <3EDDDAC7.7030005@comsys.se>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Hi All,

Can any one kindly answer my query? I want to know if the MOS switches and other lowest-level primitives that verilog supports are used by any one, either in their simulation environment or in their RTL code. If YES, then where exactly are they being used?

Thanks in Advance!

R Ramakrishna

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Follow-Ups:
- Re: [oc] Query abt Switch level modelling in Verilog
  - From: John Sheahan <jrsheahan@optushome.com.au>

References:
- [oc] I thought that this might be interesting.
  - From: Lars Segerlund <lars.segerlund@comsys.se>

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