Re: [oc] Query abt Switch level modelling in Verilog

[John Sheahan <jrsheahan@optushome.com.au>]

On Mon, 2003-06-16 at 22:44, R. Ramakrishna wrote:
> Hi John,
>  
> Thank you for the information.
> But please let me know if the gate level primitives are being used by any 
> one to try and emulate the hardware test environment to max possible
> extent, for example, using rcmos in place of pullup to model a very
> week pull-up on a net or in generating an SDRAM model at switch level
> or something else.

being picky - I'd guess the SDRAM model to be behavioural, or perhaps 
RTL. Not (much) primitive.  The pullup is difficult to model well in
verilog for timing reasons.  But these are details - the concept is
right.  

> Also, I believe these basic switches are not synthesizable and are just meant for simulating hardware-- please correct me if I am wrong.

That is my understanding.
for example
Your silicon vendor will supply you with a gate library which may be
made partially of primitives for simulation.  The gates themselves are
blocks available to the synthesis tool selected on some kind of pure
behavioural basis. Library gates are a synthesis tools prmitives,  not
the same thing as the verilog primitive set.


primitives also allow extension in unusual directions.


>  
> Thanks and regards,
> R Ramakrishna
> 

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