Re: [oc] The use of both edge of the clock.

[Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>]

>>>>> "Nico" ==   <nico@seul.org> writes:

    Nico> At school, we learn that design must be full synchronous on one
    Nico> edge of the clock to avoid any timing hasard.

    Nico> But, i see very often some chip interface that sample or deliver
    Nico> the data at the folling edge of the clock. Does this trick very
    Nico> usefull ? Does it generate dozen of "false path" for synthetiser ?

On the inside of of chips, you can probably always split the pathes and use
posedge and negedge. To have off chip signal on both edges (dual rate in the
PC slang), you nned (FPGA) hardware that copes with that. E.g. Xilinx
Coolrunner II and Virtex2/2P/Spartan3 has such IO structures. 


    Nico> What is the common rules and pitfall about using this ?

Not enogh experience here.

Bye
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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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