Re: [oc] vhdl question

[spyros <spyros_s@freemail.gr>]

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put an OR gate and condition this for start to stay high, perhaps?
example:

- ---cut here---

signal mid : std_logic;

mid <= start OR clk;
start <= '1' when mid='1' and addr(7 downto 0)="11111111" else '0';

- ---cut here---

keep start to '1' as many cycles you need to.
regards,
spyros

Saumil Merchant wrote:
 > Hey guys,
 > I had a question. I have a combinational statement in VHDL as given 
below.
 >
 > start <= '1' when read='1' and addr(7 downto 0)="11111111" else '0';
 >
 > Now what happens here is that read goes high only for one clock cycle
 > and hence so does start. How can I make start stay high for 2 or more
 > clock cycles and then go low ?
 >
 > -----------------------------------------------------------------
 > Saumil Merchant
 > University of Tennessee
 > http://web.utk.edu/~smerchan
 > -----------------------------------------------------------------


- --

student @ D.U.TH.

pub-key: http://dalab.ee.duth.gr/~spyros/my_pub.asc


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