Re: [oc] Output loading in digital circuit

["Kenneth Hung" <hungwaiming@hotmail.com>]

No my question is why the datasheets in many logic design has such output
loading.
I understand loading would cause effects but how these values come about ?
Seems no one understand this before doing real design.


----- Original Message -----
From: "John Sheahan" <jrsheahan@optushome.com.au>
To: <cores@opencores.org>
Sent: Friday, March 29, 2002 6:03 AM
Subject: Re: [oc] Output loading in digital circuit


> On Thu, Mar 28, 2002 at 06:05:12PM +0800, Kenneth Hung wrote:
> > Hi all guys
> >
> > I am a digital circuit designer. However, I am always confusing why
> > in the datasheet spec, there're output loading with different values.
> > Say 50pF and 500ohm in parallel with the output.
>
> remember, gates are analog things made of real transistors.
> they get to drive real bits of wire.
> That load causes even more deviation from the model of digital
> behaviour you rely on (as a digital designer) than usual.
> Use spice to help see more.
> But don't model a package IO too carefully, it might upset you.
>
> john
>
> >
> > Can anyone suggest why it's the case ? And how to analyse this ?
> >
> > Thanks
> > kenneth
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