Re: [oc] I2C slave model

[vikasakalwadi@rediffmail.com]

hey Richard thanks for promptly answering. My master module was tested
today on the FPGA board and the slave did acknowledge for address 4A,
so everything is perfect now. So it is sure that the behavioural slave
module has a serious problem as i had stated earlier that, its slave
address is not actually generic. Precisely speaking, when the slave
address has msb as 0, the slave does not acknowledge. Sice i do not
know verilog i cannot point out where exactly there is problem. Please
correct it, if the bug does exist.
Thanking you again,
regards,
Vikas

----- Original Message ----- 
From: Richard Herveille <richard@a... > 
To: cores@o...  
Date: Thu, 28 Mar 2002 19:25:03 +0700 
Subject: Re: [oc] I2C slave model 

> 
> 
> 
> >      Hey my slave's address is 4A, and i thought by changing 
> the 
> >parameter in your slave module to 4A, it will give the 
> behaviour of 
> >required slave. 
> 
> Euh yes. 
> It doesn't ??? 
> 
> >  If your slave does not do so, then what is the use of 
> >having the address as parameter then ? Please respond at the 
> earliest. 
> > 
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