Re: [oc] Output loading in digital circuit

[John Sheahan <jrsheahan@optushome.com.au>]

On Thu, Mar 28, 2002 at 06:05:12PM +0800, Kenneth Hung wrote:
> Hi all guys
> 
> I am a digital circuit designer. However, I am always confusing why
> in the datasheet spec, there're output loading with different values.
> Say 50pF and 500ohm in parallel with the output.

remember, gates are analog things made of real transistors.
they get to drive real bits of wire.
That load causes even more deviation from the model of digital 
behaviour you rely on (as a digital designer) than usual.
Use spice to help see more.   
But don't model a package IO too carefully, it might upset you.

john

> 
> Can anyone suggest why it's the case ? And how to analyse this ?
> 
> Thanks
> kenneth
> --
> To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml