[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [oc] modulo arithmatic hardware
The difference between CAM and SRAM
Assume you have a conversion function requirement where you input X and
output Y.
One way to do this is to use an SRAM (or portion thereof) that has one entry
for
every possible value of the input value and the contents for each location
contains
the result value. in C++
output = table[input];
This is an acceptable practice as long as the table size is not too large.
Suppose that the number of input values is too large for using SRAM
(requires more SRAM than you are willing to use). Also assume that
a large percentage of translations can be reduced to a set of 10 or so
most recently used entries. For those input values in the list the operation
is fast, for those entries not in the list the operation is slow. Also when
value not in list you can replace other member in list with new entry.
A typical experience for application programmers would be your
application would have multiple I/O buffers for use as a data cache.
Each I/O buffer would have a control structure indicating items such
as base address, size, dirty, reference sequence, etc...
As a request for data comes in you would compare the address requested
against the information in each buffer control structure until you found
a match or determined that the data was not in any of the buffers. In
this case you would retire a buffer and reuse it for the new entry.
For your SRAM translation function you could do this same process
where you would have an array of {input value, output value}. You
would search this array for a matching input value and if found you
would return the output value. If not found then you would take
"the long route" to find the value.
If you examine the above process you will find that the larger the
table you have then the longer on average will be the search.
This is not always desirable.
CAM does this differently. For CAM you load up a table similar
to the array of {input value, output value}. The difference though
is each entry in the CAM contains a comparitor. You locate the
result by presenting the input value to the CAM instead of searching
the array and the CAM produces the output value or indicates not
found. (and perhaps found more than once).
Look at http://www.altera.com and look in there IP core section.
They will describe this in better detail.
----- Original Message -----
From: "Zhichong Chen (Beijing)" <ZhichongChen@viatech.com.cn>
To: <cores@opencores.org>
Sent: Sunday, March 10, 2002 8:24 PM
Subject: ??: [oc] modulo arithmatic hardware
> hi, Jim
>
> It's seem to you are experienced in the design of CAM.
> I am interested in designing CAM, so can u explained it more carefully?
> What is the difference between CAM and SRAM.
> How CAM implemets the comparision?
> thanks.
>
> zhichong chen
>
> ??? zhichongchen
> > Communication Systems, R&D
> > VIA TECHNOLOGIES (CHINA) INC., LTD.
> > 6/F DASCOM Tower, No.9 Shangdi East Road
> > Haidian , Beijing, P.R. China 100085
> > Tel: 86-10-62963088 ext.3930
> >
>
>
> -----????-----
> ???: Jim Dempsey [mailto:tapedisk@ameritech.net]
> ????: 2002?3?9? 6:37
> ???: cores@opencores.org
> ??: Re: [oc] modulo arithmatic hardware
>
>
> Modulo N where N is power of 2 is relatively easy (logical AND).
> But, Modulo N some other modulous is often required.
> Modulo some prime number isn't all that unusual. This
> usualy can be done using division (taking remainder after division).
> Most division algorithms are implimented with shift and conditional
> subtract. Depending on size of input number and modulous this
> can be many clock cycles.
>
> If core size is of no concern a method to speed up the process
> could be to use a Content Addressable Memory core (CAM).
> Setup to perform range checking instead of exact match.
> With proper setup the CAM can be used to reduce a large
> number using a large number of bits into a smaller number
> using a smaller number of bits that produces the same result
> usinging the same Modulous function. This smaller number can
> be divided quicker or run through a second stage CAM for
> further reduction.
>
> Jim Dempsey
>
>
>
> ----- Original Message -----
> From: "John Sheahan" <jrsheahan@optushome.com.au>
> To: <cores@opencores.org>
> Sent: Friday, March 08, 2002 2:36 AM
> Subject: Re: [oc] modulo arithmatic hardware
>
>
> > How do you design a chunk of hardware that does not do
> > moduloN stuff?
> > john
> >
> >
> > On Thu, Mar 07, 2002 at 09:56:03AM -0800, jae lim wrote:
> > > Hello everyone
> > >
> > > Does anybody know how to design a modulo N(N>=16)
> > > logic that using as less clock cycle as possible?
> > >
> > > Thank you in advance.
> > >
> > > Jay
> > >
> > > __________________________________________________
> > > Do You Yahoo!?
> > > Try FREE Yahoo! Mail - the world's greatest free email!
> > > http://mail.yahoo.com/
> > >
> > > --
> > > To unsubscribe from cores mailing list please visit
> http://www.opencores.org/mailinglists.shtml
> >
> > --
> > To unsubscribe from cores mailing list please visit
> http://www.opencores.org/mailinglists.shtml
> >
>
>
> --
> To unsubscribe from cores mailing list please visit
> http://www.opencores.org/mailinglists.shtml
>
> --
> To unsubscribe from cores mailing list please visit
http://www.opencores.org/mailinglists.shtml
>
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml