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??: [oc] modulo arithmatic hardware
hi, Jim
It's seem to you are experienced in the design of CAM.
I am interested in designing CAM, so can u explained it more carefully?
What is the difference between CAM and SRAM.
How CAM implemets the comparision?
thanks.
zhichong chen
??? zhichongchen
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-----????-----
???: Jim Dempsey [mailto:tapedisk@ameritech.net]
????: 2002?3?9? 6:37
???: cores@opencores.org
??: Re: [oc] modulo arithmatic hardware
Modulo N where N is power of 2 is relatively easy (logical AND).
But, Modulo N some other modulous is often required.
Modulo some prime number isn't all that unusual. This
usualy can be done using division (taking remainder after division).
Most division algorithms are implimented with shift and conditional
subtract. Depending on size of input number and modulous this
can be many clock cycles.
If core size is of no concern a method to speed up the process
could be to use a Content Addressable Memory core (CAM).
Setup to perform range checking instead of exact match.
With proper setup the CAM can be used to reduce a large
number using a large number of bits into a smaller number
using a smaller number of bits that produces the same result
usinging the same Modulous function. This smaller number can
be divided quicker or run through a second stage CAM for
further reduction.
Jim Dempsey
----- Original Message -----
From: "John Sheahan" <jrsheahan@optushome.com.au>
To: <cores@opencores.org>
Sent: Friday, March 08, 2002 2:36 AM
Subject: Re: [oc] modulo arithmatic hardware
> How do you design a chunk of hardware that does not do
> moduloN stuff?
> john
>
>
> On Thu, Mar 07, 2002 at 09:56:03AM -0800, jae lim wrote:
> > Hello everyone
> >
> > Does anybody know how to design a modulo N(N>=16)
> > logic that using as less clock cycle as possible?
> >
> > Thank you in advance.
> >
> > Jay
> >
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