Re: [usb] DPLL in USB2.0

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-02-19 at 10:39, henry_xb wrote:
> Hi friends！
> 
> The Dpll in Usb2.0 use a statemachine to detract the data and clock ,Can tell me how it works?

Really ?!  You should tell us how it works !
Or search the usb.org site yourself to find the white
paper that explains it ...

Lets, see, data rate about 480 Mbit/s, 4x oversampling (not sure
if that meets USB 2.0, but just for this argument ...), would
mean 1920MHz clock for your state machine !

I guess full custom circuit in 0.13u ?

Wouldn't an Analog PLL be a better choice ?

I think you know of some secrets we don't know ! :*)

> 		
> Best Regard
>  
> 				 
> 　　　　　　　　henry_xb
> 　　　　　　　　xxiaobin@263.net
> 　　　　　　　　　　2003-02-19
> 


Cheers !
rudi
------------------------------------------------
www.asics.ws   - Solutions for your ASIC needs -
FREE IP Cores  -->   http://www.asics.ws/  <---
-----  ALL SPAM forwarded to: UCE@FTC.GOV  -----




--
To unsubscribe from usb mailing list please visit http://www.opencores.org/mailinglists.shtml