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[oc] To Jason


Hello Jason 

Thank you very much for your input!


> A better approach might be to design the pipeline
> with various points at which the execution could be
> registered and turn them on or off using synthesis 
> directives and GENERICS.Thus for different FPGA 
> architectures and synthesis tools the code could be 
> optimized to have the best performance.


How can I design the pipeline at different points at
which the execution could be registered? What is
GENERICS?
 
And also, about the control logic, could you explain
to me in more detail? I am really new to this area:--(

THanks again and have a nice weekend.

Xia 

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