Re: [oc] synthesize and pipeline programming

[Richard Herveille <richard@asics.ws>]

If you use a synthesis tool that is capable of retiming many of the points 
described are taken care of by the tool.
Retiming means actually moving logic between register stages.

Example

<reg1> - <small logic block> - <reg2> - <big logic block> -  <reg3>

In this case the big logic block determines the speed of the system (assuming 
kinda linear delay depending on the amount of logic, not always true though). 
Retiming means moving logic from the big block into the small block, thus 
creating two new blocks that have (almost) the same delay. Compared to the 
original delay, the delay will be more for the small logic block, but less 
for the big logic block. Thus increasing the total speed of the system.

Richard

> If your goal is to optimize each stage of the pipeline
> then you will have to repeat the synthesis of the verilog.
> After each synthesis, evaluate the timing and try and
> optimize the stages to meet your design requirements or
> balancing of the pipeline stages (if an optimal approach
> is desired...)
>
> Each stage of a pipeline is defined by the registering of
> signals within that stage... If the signals are registered
> between each stage, you will not get any major optimizations
> between stages. Synthesis tools don't generally move logic
> (maybe inverters) from one side of a flip-flop to the other...
>
> Ultimately it all depends on what your goal is...
>
> Depending of what FPGA architecture and what systhesis tool &
> synthesis directives the end-user is using, the stages will have
> different timing and thus the overall performance will differ...
>
> A better approach might be to design the pipeline with various
> points at which the execution could be registered and turn them
> on or off using synthesis directives and GENERICS.  Thus for
> different FPGA architectures and synthesis tools the code
> could be optimized to have the best performance.
>
> Examples of this kind of coding exist in GNU Software...
> For different architectures and different Operating Systems
> the code compiles differently to take advantage of specific
> optimizations available at compile-time...
>
> As always though, the control will be a bit of a pain...
> Some control signals will have to be delayed until needed
> by a specific "stage" and others might not be needed at all.
> This is most apparent in the register dependency logic
> between stages...
>
> If I am mistaken in any of my assumptions please correct me...
> I haven't paid very close attention to synthesis tools for
> a few years, but I don't think they have changed that much...
>
> --- Madhusudhan Rao <madhu_sudhana_rao@yahoo.com> wrote:
> >     1. If you want to better optimization in your
> > pipeline case better to synthesize as single module.
> > If u synthesize individually Design Compiler will take
> > care about individual stage optimigation only.
> >
> > --- jae lim <jlim0011@yahoo.com> wrote:
> > > 1) For the pipelined Simple RISC processor, is it
> > > easier for the synthesis tool to optimize the code
> > > if I implemented as five stage pipeline as small
> > > modules as possible or it doesn't matter even if I
> > > implement it as a whole big module? If the former is
> > > the case, should I divide the module as five stages,
> > > including every functional units into the stage
> > > modules or should I put the functional units as
> > > individual modules?
> > > Any suggestions will be greatly helpful!!
> > >
> > > Have a nice weekend.
> > >
> > > Jay
> >
> > =====
> > MadhusudhanaRao.M
>
> God Bless,
> ---
> Jason Silcox
>
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