[oc] module instantiation

[jae lim <jlim0011@yahoo.com>]

Hello Everyone

I have some questions about the module instantiation
in Verilog. Suppose I have three modules, the
RANDOMGEN module, which is to generate random number,
RANDOM, using LFSR; the second one is MODULO module,
which is to round the RANDOM to the limited range,
let's say the final random number out of the modulo is
REMINDER; the third one is ARBITER module, it is used
to implement the arbitration algorithm which will use
the random number REMINDER generated by MODULO module.
OK, in this case, should I instantiate the RANDOMGEN
module in the MODULO module, and the MODULO module in
the ARBITER module or, I should instantiate all the
modules in the TEST_TOP, which is the highest test
bench module?

And one more thing, how should I keep the timing? When
the RANDOM is generated and then generate REMINDER,
and when REMINDER is generated, then start arbitrate. 

Thank you all for the help!!

Jay 


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