RE: [oc] Silicon Implementation

["Morris, Scott J" <morris.scott@pnl.gov>]

Just a note about Quicklogic.  They will send out free samples for many of
their chips.  You send them a programming file and they send you a few
programmed chips.  Not all their chips are available through this but if
this is just a hobby then it may be a good route.

As far as speed I've designed a design for a QL3060 speed -3 that has 16
12-bit counters all running at 100MHz.  Now that's all I needed but the path
analyzer said I could run them upto around 200 MHz and that's without any
optimizaion for that path and that is not their fastest chip.

I've used quicklogic for many designs and have been satisfied for the most
part.  

Scott

> -----Original Message-----
> From: Ali Mashtizadeh [mailto:ali@alikat.org]
> Sent: Tuesday, March 12, 2002 4:53 PM
> To: cores@opencores.org
> Subject: Re: [oc] Silicon Implementation
> 
> 
> John Sheahan wrote:
> > 
> > On Tue, Mar 12, 2002 at 07:48:54AM -0800, Ali Mashtizadeh wrote:
> > 
> > I forgot to mention the scan , membist and jtag tools tools needed
> > for the asic too.
> > >
> > > Can you suggest a FAST FPGA that uses Antifuse or NVRAM? 
> 300K to 500K.
> > > Cheap and low power? Price is more important than power I 
> will probably
> > > have to use a Li-ion battery anyways.
> > 
> > Can you give me a hint as to what 'fast' is here and how 
> many registers may
> > clock at that rate?  approx how many IO, what flavor, what speed.
> about 150 IO pins, and I would like to operate my design at 
> 200-300Mhz.
> I've synthesized my parts and the largest delay seems too limit the
> design to a little 100Mhz on a Spartan II 200K.
> > 
> > 400k asic gates would be 20Kff's, but if you are using
> > fgpa accounting could be less.
> I'm using an estimate from Xilinx Spartan II since I havn't 
> synthesized
> the whole thing and my estimate based on how much the parts take
> seperately shows I need about 300K - 500K gates. (I have two 
> projects).
> 
> > Actel have biggish antifuse stuff.
> Yes, actel's the best I've found so far, I'll have too wait until they
> reach their goal in a couple of months for the lower end 
> ProAsic+ since
> the price of those are a lot better than what I've seen for quicklogic
> and it's fast with pleanty of block ram for cache and tlb etc. I was
> looking for 10KBs or so and their close and even more than enough if I
> get the APA450. Do you have any experience with actel chips that you
> could compare the performance/density between actel proasic and some
> xilinx chip (Spartan II or Virtex).
> 
> > Cypress has ee stuff that large.
> I'll check them out.
> > quiklogic has/had some interesting stuff too.
> Quicklogic's too expensive, Prices are a lot steeper than xilinx.
> 
> > 
> > the sram based things (eg virtex or spartan out of Xilinx, apex and
> > acex out of Altera is a two chip solution, not one,  but usually is
> > lower power.    I [refer these architectures.
> > some of them now have encrypted bitmaps for security if thats the
> No, I just want instant on feature and don't you have to keep the FPGA
> with a battery to power the decryption key?
> 
> > issue.  Soldering down those ball grids will be a pain.
> Ball grids aren't that bad. Just heat them up from under the board and
> they just sink in, it's a pain getting it in the right 
> position though.
> 
> > 
> > I'm sure there are a bunch more I've not looked at or forgotten..
> > 
> > john
> > 
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