Re: [oc] I2C slave model

[John Sheahan <jrsheahan@optushome.com.au>]

On Thu, Mar 14, 2002 at 06:06:49AM +0100, Richard Herveille wrote:
> 
> >hi,
> >i had developed a simple i2c bus master in VHDL and was using I2C
> >slave verilog code taht was available over here for the purpose of
> >testing. When i am giving the start, and the address of the slave, the
> >slave is not generating the acknowledgement bit. Since i donot know
> >verilog, i couldnot figureout why such problem came up.
> >Shouldn't the slave send an acknowledgement bit after the master
> >addresses it ?
> 
> Yes it should.
> 
> > If yes, can anybody let me know it the verilog slave
> >code available over here would respond with the acknowledement bit or
> >not ?
> 
> And yes it does. The testbench for the i2c_master_core tests this bit.
> 
> Richard

agree that the i2c verilog slave model does drive ack. but there is
the odd race in the model, as I noted a while back. What do I do with the
fixes?   The current one does not work with several simulators I tried.y

john
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