Re: [oc] WISHBONE ack_o signal imlpementation

[Rudolf Usselmann <rudi@asics.ws>]

On Saturday 03 November 2001 19:30, you wrote:
> I have a question about imlpementing WISHBONE's ack_o signal in verilog.
>
> I have the following need:
> 1. One wait state (ack_o) is returned one clock after stb_i and cyc_i
> are asserted.
> 2. The ack_o should be asserted for one clock only and go down when
> stb_i goes down (required by WISHBONE spec).

It may be asserted for multiple cycles during a burst. 

> 3. It should not toggle in long cycles.
>
> There are no other clocks except the wishbone bus clock.
>
>
> The simplest imlpentation:
> 1)
> wb_ack_o <= #1 wb_cyc_i & wb_stb_i;
> does one clock delay but it also delays the deassertion of wb_ack_o for
> one clock too.
>
> So, the following seemed like a good idea:
> 2)
> wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;
> It was ok until David C.Davies pointed me out that on long cycles
> (longer than 1 or 2 clock cycles) it toggles.

This is probably what you want. Depending on the rest of your core
you might want for it to toggle. Think of the case where the master does
a burst read or write.

> Looking at the WISHBONE spec I found that WISHBONE master should
> deassert its cyc_o and stb_o next clock after receiving ack_i. That way
> David's description of long cycles seems to be violating the rules of
> WISHBONE.

It does not have to deassert cyc and stb if it wants to do consecutive 
read/write cycles. It would be perfectly legal to keep cyc and stb
asserted and only change the address after each ack.

rudi

> In that case the second implementation seems to be the right one.
>
> Am I right on this?
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