Re: [oc] WISHBONE ack_o signal imlpementation

["Andras Tantos" <andras_tantos@yahoo.com>]

Hi!

> I have a question about imlpementing WISHBONE's ack_o signal in verilog.
>
> I have the following need:
> 1. One wait state (ack_o) is returned one clock after stb_i and cyc_i
> are asserted.
>...
> Looking at the WISHBONE spec I found that WISHBONE master should
> deassert its cyc_o and stb_o next clock after receiving ack_i. That way
> David's description of long cycles seems to be violating the rules of
> WISHBONE.
>
> In that case the second implementation seems to be the right one.
>
> Am I right on this?

Yes, you are right. As far as I know if the master does not remove STB_I
and/or CYC_I signals after receiving an acknowledge, it is considered a new
cycle. There is no easy way to determine if the address or the data has been
changed anyway so you cannot but repeat the whole cycle with all wait-states
involved in it.

Regards,
Andras Tantos


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