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Re: [oc] [FPGA] topology search

To: <cores@opencores.org>
Subject: Re: [oc] [FPGA] topology search
From: "Marko Mlinar" <Marko.Mlinar@campus.fri.uni-lj.si>
Date: Sat, 31 Mar 2001 19:35:39 +0200
Organization: FRI
References: <001201c0b906$8f1f2820$bf4902c1@Javor> <3AC5DF71.1080600@spth.de>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org



> 19260 (1,0) (11,7) (7,3) (13,11) *nbest 1000, total_cost 8,93
Thank you. 
I see numbers are pretty large - lets suppose LCs have 80x80um
in size, does anyone here know (or can estimate) what is extra
delay per additional wire length for 80um.
I am saying this, because it would be surely better to have
shorter connections with same cost. Also this would decrease FPGA
size. Maybe I should increase cost for longer connections?

Marko

References:
- [oc] [FPGA] topology search
  - From: "Marko Mlinar" <Marko.Mlinar@campus.fri.uni-lj.si>
- Re: [oc] [FPGA] topology search
  - From: Philipp Krause <pkk@spth.de>

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