Re: [oc] Beyond Transmeta...

[John Dalton <johnd@southern-poro.com>]

As pointed out by Jecel, this idea bears many simliarities to an FPGA. Each
logic block in the FPGA corresponds to a "processor" and the configuration
bits (SRAM in a Xilinix) could be looked at as a form of instruction register.
To my thinking, such a device falls into the field of "reconfigurable computing",

a field in which I am NOT an expert.

To my understanding, reconfigurable computing involves configuring an
SRAM based FPGA on the fly to perform a computation.  The few systems
I have heard of involve a host processor configuring an external FPGA.
Leyland's idea suggests taking this a step further and building a
"self-modifying"
FPGA, which requires no external processor, as it IS the processor.  For all I
know, this might have already been done.

Each logic cell could have a queue from which configuration data
("instructions") are read.  These queues could be preloaded with a static
program.  Alternatively, the outputs of the logic blocks could be connected
to the inputs to the queues.   One could imagine programming a portion
of the FPGA with a compiler program (gcc?).  This would then generate
instructions which are executed by some other portion of the FPGA. (Note
all sections fo the FPGA are identical in that they are just logic blocks.)
The result would be an FPGA that can execute a C (or insert your preferred
language) program!

Routing may be an issue.  In an FPGA not every logic block can communicate
with every other logic block.  An analogy with a traditional CPU would be
that an operation on memory location 'x' can only involve memory
cells in the range 'x-n' to 'x+m'.  Assembly language would be a nightmare,
but a smart compiler could hide this limitation from the user.  I would
not like to be the programmer porting the first compiler to the chip!  Then
again, it would be a really interesting project.

Regards
John Dalton