Re: [pci] pci core status

["MikeJ" <mikej@freeuk.com>]

sounds good,
rtl/vhdl would be my choice I think. The test bench and behavioural stimulus
could go there as well, or in bench/vhdl - not fussed.
I've also got a development board - but, likewise, time has been the issue.
Regards,
MikeJ.

----- Original Message -----
From: "Miha Dolenc" <mihad@opencores.org>
To: <pci@opencores.org>
Sent: Monday, September 17, 2001 2:43 PM
Subject: Re: [pci] pci core status


> Hello!
>
>     I think that it would be reasonable to create new directory under pci
> project directory - like
> bench/vhdl for your vhdl simulation models or rtl/vhdl for design files.
The
> whole pci project repository will be rearranged soon, since me and Tadej
are
> already running our design in insight's development board and debugging
it,
> so a lot of files will be uploaded shortly. We work in verilog, so we will
> also create directories  rtl/verilog and bench/verilog and upload files.
>
> Otherwise I'm sorry I didn't reply to all these mails for a long time - I
> had some problems with E-mail access and a lot of work to do.
>
> Regards,
>     Miha Dolenc
>
> ----- Original Message -----
> From: "MikeJ" <mikej@freeuk.com>
> To: <pci@opencores.org>
> Sent: Sunday, September 16, 2001 9:42 PM
> Subject: [pci] pci core status
>
>
> > Just a quick update chaps.
> >
> > I've got hold of the 2.2 PCI spec now, and have found that the
simulation
> > models I got from Opencores (ms32pci etc) don't allow me to test the
core
> > sufficiently- especially with regards to fast back to back transfers and
> > output enable timing.
> > I've almost finished writing my own, and I would like to upload the
> > simulation suite (vhdl) shortly so somebody else can check for any
errors
> !
> > How would I go about doing this ?
> > Could we set up a new directory for the vhdl core and test set?
> >
> > Cheers,
> > MikeJ
> >
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> >
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