[pci] Address decode

[Duane Clark <dclark@leewardfpga.com>]

Howdy,

Since we have been discussing Xilinx specific logic, here is my take on 
fast address decoding. You might want to take a look at how your 
synthesis tool is creating the decoder. If it is not using the dedicated 
carry logic, then you might want to "help" it :-)

Here is how I was doing address decoding. It is blazing fast. By the 
way, both it and the parity scheme I mentioned should be capable of 
meeting the timing for 66MHz PCI.

Duane


library ieee ;
--synopsys translate_off;
library xilinx;
use xilinx.vcomponents.MUXCY;
--synopsys translate_on;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity hit is
    port (
       CLK      : in std_logic;
       RESET    : in std_logic;
       A        : in std_logic_vector(17 downto 0);
       B        : in std_logic_vector(17 downto 0);
       FRAMEn_F : in std_logic;  -- Unregistered FRAME from pin
       FRAMEn_C : in std_logic;  -- Registered FRAME from pin
       IDSEL    : in std_logic;
       MEM_EN   : in std_logic;  -- from device control register
       CMD      : in std_logic_vector(3 downto 0);
       START    : out std_logic;
       HIT      : out std_logic
    );

end entity;

architecture synthesis of hit is
    component MUXCY
       port (
          DI    : in std_logic;
          CI    : in std_logic;
          S     : in std_logic;
          O     : out std_logic
       );
    end component;

    signal anda    : std_logic_vector(8 downto 0);
    signal muxin   : std_logic_vector(9 downto 0);
    signal muxdi   : std_logic;
    signal decdi   : std_logic;

    signal START_I : std_logic;
    signal MEMCMD  : std_logic;
    signal MEMDEC  : std_logic;
    signal MEMHIT  : std_logic;
    signal CFGHITn : std_logic;
    signal DECHIT  : std_logic;

begin

    START <= START_I;

    muxin(0) <= '1';  -- the start of the carry chain
    muxdi <= '0';    -- ground the DI input
    decdi <= '1';    -- pull high the DI input

    addr_dec: for i in 0 to 8 generate
       anda(i) <= (A(2*i) xnor B(2*i)) and (A(2*i+1) xnor B(2*i+1));

       ad_carry: MUXCY
          port map (
             DI => muxdi,
             CI => muxin(i),
             S  => anda(i),
             O  => muxin(i+1)
          );
    end generate;

    STARTP: process (CLK, RESET)
    begin
       if RESET = '1' then
          START_I <= '0';
       elsif rising_edge(CLK) then
          START_I <= FRAMEn_C and not FRAMEn_F;
       end if;
    end process STARTP;

    MEMCMD <= (((CMD(0) or CMD(1)) and CMD(3)) or (cmd(1) and cmd(3))) 
and cmd(2);

    memdec_carry: MUXCY
       port map (
          DI => muxdi,
          CI => muxin(9),
          S  => MEMCMD,
          O  => MEMDEC
       );

    memhit_carry: MUXCY
       port map (
          DI => muxdi,
          CI => MEMDEC,
          S  => MEM_EN,
          O  => MEMHIT
       );

    CFGHITn <= IDSEL and CMD(1) and CMD(3) and not CMD(2);

    dechit_carry: MUXCY
       port map (
          DI => decdi,
          CI => MEMHIT,
          S  => CFGHITn,
          O  => DECHIT
       );

    hit_carry: MUXCY
       port map (
          DI => muxdi,
          CI => DECHIT,
          S  => START_I,
          O  => HIT
       );

end architecture synthesis;




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