5. Tcl Interface

5. 1. General

5. 1. 1. Configuration

avt_Config

void avt_Config(char *var, char *val)

Main way to configure the tool. Affects a value to one of the variables listed in the Configuration Variables section

var Configuration variable to be set
val New value
EXAMPLE avt_Config tasGenerateConeFile yes


avt_GetConfig

char *avt_GetConfig(char *var)

returns the configurated value for configuration variable var

var Configuration variable to be set
EXAMPLE set cone_cfg [avt_GetConfig tasGenerateConeFile]


5. 1. 2. File Loading

avt_SetBlackBoxes

void avt_SetBlackBoxes(List *list)

Allows the user to blackbox subcircuits. Blackboxed subcircuits will not be analyzed. Instead, the tool will let a hole. Whether this hole should be filled up or not by a timing description depends on configuration variables tasIgnoreBlackbox and tasTreatBlackboxHierarchically. If a blackbox name is prefixed with "unused:", no hole will be created but instead all transistors in the blackbox will be marked as unused. Those blackboxes can still be retreived with GNS if the recognition rule uses the same transistor names as in the blackbox. This command is equivalent to and overrides the creation of a BLACKBOX file.

list List of subcircuits to be blackboxed. All intended blackboxed subcircuits should present as only one avt_SetBlackBoxes command is allowed.
EXAMPLE avt_SetBlackBoxes [list "sense_amp"]


avt_LoadBehavior

BehavioralFigure *avt_LoadBehavior(char *filename, char *format)

Loads behavioral descriptions and construct internal representation according to the file format

filename File to be loaded
format Available formats are vhdl and verilog
EXAMPLE avt_LoadFile model.v verilog


avt_DriveBehavior

void avt_DriveBehavior(BehavioralFigure *befig, char *format)

Drives a behavioral description according to the file format from the given internal representation

befig Behavior to be driven
format Available formats are vhdl and verilog
EXAMPLE avt_DriveBehavior $befig output.v verilog


avt_LoadFile

void avt_LoadFile(char *filename, char *format)

Loads files and construct internal representation according to the file format

filename File to be loaded
format Available formats are spice, tlf4, tlf3, lib, verilog, vhdl, spf, dspf, inf, spef and ttv
EXAMPLE avt_LoadFile design.hsp spice


avt_EncryptSpice

void avt_EncryptSpice(char *inputname, char *outputname)

Encrypts all sections of a Spice file (netlist or technology file) which are encapsulated by the .protect and .unprotect spice cards.

inputname File to be encrypted
outputname Destination for encrypted output
EXAMPLE avt_EncryptSpice techno.hsp techno.hsp.enc


avt_SetCatalog

void avt_SetCatalog(List *argv)

Sets the leaves when flattening a netlist to catal level; equivalent to create a CATAL file

argv List of subcircuits that will be used as leaves
EXAMPLE avt_SetCatalog [list "nand2" "inv" ]


avt_GetCatalog

StringList *avt_GetCatalog()

Returns the current list of cells set as leaves for a catal-level flatten

EXAMPLE set catal [avt_GetCatalog]


avt_CheckTechno

void avt_CheckTechno(char *label, char *tn, char *tp)

Runs a set of benchs to findout possible technology errors

label A prefix label for the output result files
tn NMOS transistor characteristics. It's a space separated string with coming first the NMOS transistor name followed by the parameters. Authorized parameters are: l, w, delvt0, mulu0, sa, sb, sd, nf, nrs, nrd, sc, sca, scb, scc.
tp same as tn for PMOS transistor.
EXAMPLE avt_CheckTechno check1 "nmos l=0.4u w=0.8u" "pmos l=0.4u w=1.6u"


5. 1. 3. Netlist Modification

avt_GetNetlist

Netlist *avt_GetNetlist(char *name)

Retrieves a netlist from memory and returns its pointer

name Name of the netlist to get in the program's memory
EXAMPLE set netlist [avt_GetNetlist "my_design"]


avt_FlattenNetlist

void avt_FlattenNetlist(Netlist *lf, char *level)

Flattens a netlist to a given level.

lf Pointer on the netlist to be flattened
level Hierarchical level (coming from top-level) the nelist will be flattened to. Available levels are trs, catal or bbox (transistor, catalog or blackbox). If none of those levels are used, level will be considered an instance name, to which the netlist will be flattened.
EXAMPLE avt_FlattenNetlist $netlist trs


avt_DriveNetlist

void avt_DriveNetlist(Netlist *lf, char *filename, char *format)

Saves the netlist on disk according to the given format

lf Pointer on the netlist to be saved
filename Name of the file to be created
format Available formats are spice, verilog, vhdl and spef
EXAMPLE avt_DriveNetlist $netlist design.spi spice


avt_DisplayNetlistHierarchy

void avt_DisplayNetlistHierarchy(FILE *f, char *netlistname, int maxdepth)

Displays hierarchy information of a given netlist, and other info such as number of transistors

f Pointer on the file where to save information, for standard output set stdout
netlistname Pointer on the netlist
maxdepth Maximum hierarchical depth coming from top level; can be set to 0 for infinite depth
EXAMPLE avt_DisplayNetlistHierarchy stdout "my_design" 3


avt_DisplayResistivePath

void avt_DisplayResistivePath(FILE *f, Netlist *lf, char *connector1, char *connector2)

Displays one resistive path between two connectors at the interface of a netlist.

f Pointer on the file where to save information, for standard output set stdout
lf Pointer on the netlist
connector1 first connector name
connector2 second connector name
EXAMPLE avt_DisplayResistivePath stdout [avt_GetNetlist "mynetlistname"] vdd_0 vdd_1


avt_RemoveResistances

void avt_RemoveResistances(Netlist *lf, char *nameregex)

Removes all resistances on signals matching a regular expression

lf Pointer on the netlist where to remove resistances
nameregex Regular expression to be matched, for all signals use *
EXAMPLE avt_RemoveResistances $netlist "cpu.*.sig3*"


avt_RemoveCapacitances

void avt_RemoveCapacitances(Netlist *lf, char *nameregex)

Removes all capacitances on signals matching a regular expression

lf Pointer on the netlist where to remove capacitances
nameregx Regular expression to be matched, for all signals use *
EXAMPLE avt_RemoveCapacitances $netlist "cpu.*.sig3*"


5. 1. 4. Statistics

avt_StartWatch

void avt_StartWatch(char *name)

Starts a timer; if the timer already exixts it'll be reset to 0.

name Timer name
EXAMPLE avt_StartWatch "CPU_TIME"


avt_StopWatch

void avt_StopWatch(char *name)

Stops a timer; the timer must be started for the function to work

name Name of the timer to stop
EXAMPLE avt_StopWatch "CPU_TIME"


avt_PrintWatch

char *avt_PrintWatch(char *name)

Returns a string with the value of a timer; the timer must have been started

name Name of the timer to print
EXAMPLE avt_PrintWatch "CPU_TIME"


avt_GetMemoryUsage

long avt_GetMemoryUsage()

Returns an integer with the memory usage of the program in bytes

EXAMPLE set memory [avt_GetMemoryUsage]


avt_RegexIsMatching

int avt_RegexIsMatching(char *nametocheck, char *template)

Returs 1 if nametocheck matches the regular expression template, 0 otherwise.

nametocheck name to check.
template regular expression to use.
EXAMPLE set match [avt_RegexIsMatching tatoo5 *too*]


5. 2. Design Specific Configuration

5. 2. 1. General

inf_SetFigureName

void inf_SetFigureName(char *name)

Sets the target figure on which to apply the INF functions

name Name of the target figure
EXAMPLE inf_SetFigureName cpu


inf_AddFile

void inf_AddFile(char *filename, char *figname)

Loads an INF file and applies included statements on a figure (this function does not invoke inf_SetFigureName).

filename INF file to load
figname Figure on which to apply INF statements. Those statements will be added to the ones that my be already present.
EXAMPLE inf_AddFile cpu.inf cpu


inf_Drive

void inf_Drive(char *outputname)

Saves applied INF statements on disk

outputname File where to save INF statements (the .inf suffix is not automatically added)
EXAMPLE inf_Drive cpu.inf


inf_ExportSections

void inf_ExportSections(char *outputname, char *section)

Saves on disk applied INF statements related to specific INF sections

outputname File where to save INF statements
section OperatingCondition, PinSlew, Rename, Stop, Sensitive, Suppress, Inputs, NotLatch, CkLatch, Ckprech, Precharge, Dirout, Mutex, CrosstalkMutex, Constraint, ConnectorDirections, PathIN, PathOUT, PathDelayMargin, MulticyclePath, Ignore, NoCheck, Bypass, NoRising, NoFalling, Break, Inter, Asynchron, DoNotCross, Transparent, RC, NORC, SIGLIST, Falsepath, Delay, Dlatch, FlipFlop, Slopein, Capaout, OutputCapacitance, SwitchingProbability, Directives, Stb and Stuck.
EXAMPLE inf_ExportSections cpu.inf "Dirout CrosstalkMutex"


inf_CleanFigure

void inf_CleanFigure()

Removes all INF statements on current figure



5. 2. 2. Netlist

inf_DefineIgnore

void inf_DefineIgnore(char *type, List *list)

The tool ignores specified components. Equivalent to commenting out elements in a SPICE netlist.

list Pointer on the list of components to ignore. An component name can be a regular expression.
type Supported types are Instances, Transistors, Resistances, Capacitances, Diodes, Parasitics and SignalNames. Parasitics affects only DSPF files. SignalNames affects only the flattening of a hierarchical netlist, by ignoring the given name if several hierarchical names are available for one net.
EXAMPLE inf_DefineIgnore Transistors *.M23*


5. 2. 3. Disassembly

inf_DefineMutex

void inf_DefineMutex(char *type, List *list)

Adds mutual exclusion constraints on signals, in order to help the disassembly process. May be especially usefull when dealing with shifters or multiplexors, in case mutual exclusion constraints can not be directly derived from internal combinational circuitry (if the mutual exclusions constraints come from latched values or come from constraints on external pins).

type Mutual exclusion constraints, legal values for are muxup, muxdn, cmpup and cmpdn (see INF file description)
list List of signals mutual exclusions constraints should be applied on
EXAMPLE inf_DefineMutex cmpup [list a_0 a_1 a_2 a_3]


inf_DefineInputs

void inf_DefineInputs(char *name)

Sets a signal as a circuit input, in order to help the disassembly process.

name Signal's name


inf_DefineDirout

void inf_DefineDirout(char *name, int level)

Defines the level of a signal for transistor orientation, in order to help the disassembly process.

name Signal's name
level Signal's level; transistors are oriented (the sense of the current is) from high-level to low-level signals.


inf_DefineDLatch

void inf_DefineDLatch(char *name)

Sets a signal as a dynamic latch. Works only if the surrounding circuitry permits a HZ state on the signal. Commands are then identified automatically.

name Signal's name


inf_DefineNotDLatch

void inf_DefineNotDLatch(char *name)

Disables a dynamic latch directive on a signal. To be used together with yagMarkTristateMemory

name Signal's name


inf_DefineNotLatch

void inf_DefineNotLatch(char *name)

Disables the identification of a latch on a signal

name Signal's name


inf_DefineKeepTristateBehaviour

void inf_DefineKeepTristateBehaviour(char *name)

Disables the transformation of bus into register when configurations 'avtVerilogTristateIsMemory' or 'yagleTristateIsMemory' is used to drive a behavioural model.

name Signal's name


inf_DefinePrecharge

void inf_DefinePrecharge(char *name)

Sets a signal as a precharge.

name Signal's name


inf_DefineNotPrecharge

void inf_DefineNotPrecharge(char *name)

Disables the identification of a precharge on a signal

name Signal's name


inf_DefineModelLatchLoop

void inf_DefineModelLatchLoop(char *name)

Feedback loop is explicitly modeled in behavioural model if signal is a static latch.

name Signal's name


inf_DefineMemsym

void inf_DefineMemsym(char *name0, char *name1)

Sets a pair of signals to be a symmetric memory so long as there is a loop between the two signals.

name0 name of first memsym signal.
name1 name of second memsym signal.
EXAMPLE inf_DefineMemsym memsym0 memsym1


inf_DefineRS

void inf_DefineRS(char *name, char *type)

Allows control of how individual RS are handled. Overrides the global setting in yagAutomaticRSDetection.

name Signal's name, either the set or the reset one is enough.
type LEGAL, ILLEGAL or MARK_ONLY.
EXAMPLE inf_DefineRS rsnode "LEGAL"


inf_MarkSignal

void inf_MarkSignal(char *name, char *marks)

Allows application of special signal markings, such as latch identification.

name Signal's name
marks For a complete list of markings please refer to the INF section of this manual, MARKSIG subsection.
EXAMPLE inf_MarkSignal dff_m "LATCH+MASTER"


inf_MarkTransistor

void inf_MarkTransistor(char *name, char *marks)

Allows application of special transistor markings, such as latch commands identification.

name Signal's name
marks Legal markings are "Bleeder", "Feedback", "Command", "NonFunctional", "Blocker", "Short", "Unused". Types may be concatenated with the '+' character and are case-insensitive. For a description of the types please refer to the INF section of this manual, MARKTRANS subsection.
EXAMPLE inf_MarkTrans m0 "FEEDBACK+NOT_FUNCTIONAL"


inf_DefineSensitive

void inf_DefineSensitive(char *name)

Sets a signal as a timing sensitive net.

name Signal's name


inf_DefineSuppress

void inf_DefineSuppress(char *name)

Sets an auxiliary signal to be suppressed.

name Signal's name


5. 3. Disassembling

5. 3. 1. yagle

void yagle(char *figname) yagle (<figname>) generates a RTL behavioral description from the transistor-level netlist given by <figname>. The netlist should exist in the program's memory (loaded with avt_LoadFile for example).