1. Software Installation
2. Overview
3. Theory Understanding
4. Scope of Usage
5. Design Flow Integration
6. Using Tcl Interface
7. Timing DB Construction
8. Timing DB Browsing
9. Static Timing Analysis
10. Crosstalk Analysis
11. Spice Deck Generation
12. Analog Sub-circuit Characterization
13. Timing Characterization (.lib)
14. Using the GUI
15. Managing Big Designs
16. Glossary

Chapter 7 Subsections

7. Timing DB Construction
7. 1. File Loading
7. 1. 1. Transistor Technology Models
7. 1. 2. Input Netlist
7. 1. 3. Parasitics
7. 2. DB Construction
7. 2. 1. Defining Power Supplies
7. 2. 2. Defining Simulation Thresholds
7. 2. 3. Defining Simulation Temperature
7. 2. 4. Invoking DB Construction
7. 3. Output Files
7. 3. 1. REP file
7. 3. 2. LOOP file
7. 3. 3. CNS, CNV files
7. 3. 4. DTX and STM files
7. 4. Latch Detection and Modeling
7. 4. 1. Detection Sequences
Manual Identification
Simple Detection
Automatic Detection
Dynamic Latches Detection
7. 4. 2. Enabling Detection Sequences
7. 5. Static Latch Modeling
7. 5. 1. Asynchronous Set and Reset
7. 5. 2. Manual Configuration
7. 5. 3. Intrinsic Setup and Hold
Intrinsic Setup
Intrinsic Hold
7. 6. RS-Latches
7. 6. 1. Modeling of NOR-based structures
All States Allowed
Legal States Only
7. 6. 2. Modeling of NAND-based structures
All States Allowed
Legal States Only
7. 6. 3. Fine Tuning
7. 6. 4. Manual Tuning
7. 7. Symmetric Latches
7. 7. 1. Symmetric Pulldown
Typical Structure
Latch Nodes and Commands
Timing Arcs
7. 7. 2. Symmetric Bitcell
Typical Structure
Latch Nodes and Commands
Timing Arcs
7. 7. 3. Asymmetric Pulldown
Typical Structure
Latch Nodes and Commands
Timing Arcs
7. 8. Dynamic Latches
7. 9. Special Elements
7. 9. 1. Transmission Gates
7. 9. 2. Transmission Gate Multiplexers
7. 9. 3. Domino Precharge
7. 10. Case Analysis
7. 11. Integrating External Timing Abstractions