[ethmac] Some revision is required in test bench code

[SUNGYON@aaww.com]

Dear Igor and any good member,

Nowadays, I am doing with open_eth simulation.

I found 2 bench bugs which make wrong FAIL report in i1_eth_tb.log

The first one is,
in the following portion of wb_slave_behavioral(.v) module,

..........................................................................................................................................
always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or
        //mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or <--
this makes wrong decision
        task_mem_wr_data or task_dat_i or // <-- this is correct
        SEL_I or task_sel_i)
begin
  if (task_wr_data)
  begin
    task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]];

    if (task_sel_i[3])
      task_mem_wr_data[31:24] = task_dat_i[31:24];
    if (task_sel_i[2])
      task_mem_wr_data[23:16] = task_dat_i[23:16];
........................ omitted
...................................................................................................

'mem_wr_data_out' or 'DAT_I' sensitivity invokes wrong write in the
wb_memory.
Received packet data must be wroten with wr_sel HIGHed to wb_memory, but
mem_wr_data_out and DAT_I transition hurts the correct data.
So almost of receive tests are being decided as FAIL. If I remove the 2
signal in the sensitivity list, It goes SUCCESS.
I think more desirable solution is to describe more detail operation of
'wb_memory'.

The other one is,
for quick location, 15973 line of in current CVS tb_ethernet.v. I think the
checking timing is somewhat earlier than tx module.
If I change the line
repeat(10) @(posedge mtx_clk);  // Wait some time for tx start.
--> repeat(50) @(posedge mtx_clk);  // Wait some time for tx start.
namely, some additional margin for expectation of tx start timing makes
SUCCESSFUL report for #3 of flow_control test.
I think the 10M testbench code and 100M testbench code should have some
difference in the case of #2 and #3 test of flow_control.

I does simulation only in ncsim run directory.

Finally, I have a question.
I think the FAIL report of #10 ~#15 of transmit test is intentional
(overflow and underflow) fail, is it right?

Regards, Sungyon.

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