Re: [usb] A student need your help

[Rudolf Usselmann <rudi@asics.ws>]

On Thu, 2003-02-20 at 00:27, elite wrote:
> Vikas,thanks for help.
> u mean the clock and the (bus) data rate are the same(480Mb/s),but I 
> want to know how it is implement(for example ,in VHDL or verilog).
> thanks!

I'm not sure you can do this with digital logic and HDL.
You will most likely use an analog PLL to lock an internal
480 MHz clock to the 480Mb/s data stream.

You can take a look at my USB 1.1 PHY, which does it with
a digital PLL to generate a 12 MHZ clock that is (almost) in
sync with the 12Mb/s data stream. That is all in Verilog.

Regards,
rudi
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