Re: [pci] Fifo instantiation in pcibridge

Hi!

Just to remind you, if you didn't do that already:

If you define PCI_XILINX_DIST_RAM and WB_XILINX_DIST_RAM,

you also have to define PCI_RAM_DONT_SHARE and WB_RAM_DONT_SHARE, since distributed RAM cannot be shared between two FIFOs - It only has one write and one read port.

You should also set PCI_RAM_ADDR_LENGTH and WB_RAM_ADDR_LENGTH to 4.

You will need RAM16X1D.v simulation model from xilinx - if you have any of their synthesis tools available, you can find it in "install_dir"\verilog\src\unisims.

You will also need glbl.v in "install_dir"\verilog\src

Hope this helps!

BTW: I get a lot of questions like this, so I think we should include this information in design document.

But I also get an impression, that this wouldn't help, since nobody will read it ;-( .

Regards,

Miha Dolenc

----- Original Message -----

From: Eric Modica

To: pci@opencores.org

Sent: Tuesday, March 12, 2002 10:00 AM

Subject: [pci] Fifo instantiation in pcibridge

Hi all,

I'm an electrical engineering student at San Jose State University. I have a question regarding the compilation of the memory blocks used as fifos in the wishbone and pci blocks. My current settings have the directives XILINX, FPGA, PCI_XILINX_DIST_RAM and WB_XILINX_DIST_RAM defined. . . So I'm wondering where I can get the memory module that is instantiated in pci_tpram.v and wb_tpram.v. I've only done some basic verilog compilations so this is all very new to me. Any help you folks can provide is much appreciated.

Thanks!

Eric