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Hi !
Miha is already verifying FIFO module, what will be somehow an interface
(or a major part of an interface) between PCI master/target and WISHBONE
slave/master.
Yesterday I meat Tilen and I gave him some advices about Verilog. Today I
think he is finishing an address decoder module (with address translation),
as described in spec.
Miha would like to do the WISHBONE slave module, when he will finish the
FIFO and I started with the WISHBONE master module.
So, if there is anybody interested to contribute to the PCI
core (PCI interface or a part of it, maybe verification, etc.), feel
free to post your message.
Whatever you contribute, will be used and all the guys that help in development, specification or verification will appear as co-authors on OpenCores webpage, if they want. Regards, Tadej.
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