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Re: [openrisc] How can i synthesize or1200?

Title:
kevin@opencores.org wrote:
hi 
    synplify show that:
"@E: sram_top.v(349): Reference to unknown variable wb_err 
@E:"e:\work\workshop\soc\or1200
\rtl\verilog\mem_if\sram_top.v":349:42:349:48".
    it looks like wb_err hasn't been defined.am i using the right version 
source file?

----- Original Message ----- 
From: ±èÈñ¿ë <hykim@d... > 
To: openrisc@o...  
Date: Thu, 19 Jun 2003 16:17:07 +0900 
Subject: Re: [openrisc] How can i synthesize or1200? 

  
Title: kevin@o...  wrote: 

 hi, i can't find the "'define SDRAM_GENERIC" in any file in the 
dictionary.when i comment the "'define SRAM_GENERIC" ,i get several 
errors.so,what can i do?where can i get a complete , synthesizable 
source code? ----- Original Message ----- From: hy kim 
<boina9456@h... > To: openrisc@o... Date: Wed, 18 Jun 2003 
15:35:15 +0900 Subject: Re: [openrisc] How can i synthesize or1200? 
 kevin@o... wrote: 
 hi,all i have got the source code from the cvs,and changed the 
"xsv_fpga_top.prj" in the "xess\xsv_fpga\orp_soc\syn\synplify" to 
let 
 synplify find the files.but when i synthezised it ,synplify told 
me several 
 files couldn't be found.then i copy those files from ".old".this 
time 
 synplify runs well.but complie takes such a long time!i waited 
half an 
 hour and stop it.my PC is P4 2.4 and 256MB memory.can anyone tell 
me 
 if this is normal? I guess that sram memory are too much. Please 
comment a line "'define SDRAM_GENERIC" in rtl/mem_if/sram_top.v and 
retry. Regards. hy kim ok not 'SDRAM_GENERIC', but 'SRAM_GENERIC' 

 and may i take your error messages? 

 regards 

 hy kim 


    
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I don't remember it exactly, and i don't use sram module no more now.
but  i remember dumly that replaced the variable 'wb_err' by 'wb_err_o'.

good lock

hy kim