[Sorry for the lag in
reply – somehow missed your message until just now.]
You could, as I
mentioned in a previous message add an acknowledgement register (PICAR) to the
PIC architecture definition. A one bit written to the PICAR would
atomically clear the corresponding bit in the PICSR. Additionally, it is
traditional to provide a similar capability to force an interrupt in software,
i.e. a new PIC register that would be OR’ed into the PICSR when it is
written.
Code written for the
existing PIC would continue to work on the “new and improved” PIC (although it
might suffer from the aforementioned race conditions if any edge-triggered
interrupts are used). Unfortunately, code designed to work with the new
PIC would not work on designs that used the old PIC. For those that are
maintaining OpenRISC SW that must work on an existing OpenRISC-based platform
as well as some later OpenRISC implementation, that could be a bit of a pain.
I think your willingness to make a change like this hinges on your perception
of how close to “1.0 release” the architecture is.
An alternate approach
would be to document in the architecture manual that the PIC, as defined, is
only suitable for level-triggered interrupts and that for edge-triggered
interrupts, an external (not defined by the architecture) interrupt controller
needs to be connected to one of the PIC’s inputs.
-----Original
Message-----
From:
owner-openrisc@opencores.org [mailto:owner-openrisc@opencores.org] On Behalf Of Damjan Lampret
Sent: Friday, February 21,
2003 8:27
AM
To: openrisc@opencores.org
Subject: Re: [openrisc] PIC
documentation
do you have a suggestion how to
keep OR1200 as it is and make definition of PIC broader to fit also the edge
triggered interrupt scheme?