|
Hello, again!
I have seen that clock gating feature in Power
Management Unit 'utomatically
disables clock subtrees to major
processor internal units on a clock cycle basis. These blocks are usually the
CPU, FPU/VU, IC, DC, IMMU and DMMU. (...) Cache or MMU blocks
that are already disabled when software enables this feature, have completely
disabled clock subtrees until clock gating is disabled or until the blocks are
again enabled'.
In
the manual, you don't specify how the clock gating feature can be disabled once
it has been enabled. If CPU have no clock, I guess that it cannot be done
by writing in Power Management Register. I wonder if clock gating feature
is disabled by an external interrupt or by a reset, or whether the
architecture allows the implementation to choose how control this
feature.
Thank
you in advance
Marķa
Bolado
|