[openrisc] how to debug memory and cache controller

["ssy" <skli@nudt.edu.cn>]

Hi dear or1k developer:

 

I want to ask a question to you, when i declare a memory block as follow:

reg    [7:0] memory [255:0];

in cache controller,How can I view its value.

 

I can not find "memory" in hierachy level view.

 

the verilog simulator of mine is VCS in workviewoffice