Re: [fpu] high performance fpu

[Rudolf Usselmann <rudi@asics.ws>]

On Thu, 2002-12-19 at 19:54, aw@gup.uni-linz.REMOVETHIS.ac.at wrote:
> hi everyone!
> 
> for my project i need a high throughput fpu. as i have to deal with rather 
> long sequences of fp-ops (nothing nasty stalling the pipe), latency is not 
> really an issue. furthermore ieee-compliance is not important as well 
> (round to -inf is the only rounding mode used) and single precision is 
> sufficent. so if anyone has good pointers to pipelined fpu designs (vhdl is 
> preferred) please drop a mail at the above adress
> 
> thanks in advance
> 
> andi

Well, the one on OpenCores is fully pipelined. You can add
more registers on the inputs and outputs to increase the
pipeline depth (use a synthesis tool that does re-timing).

rudi
------------------------------------------------
www.asics.ws   - Solutions for your ASIC needs -
NEW ! 3 New Free IP Cores this months (so far :*)
FREE IP Cores  -->   http://www.asics.ws/  <---
-----  ALL SPAM forwarded to: UCE@FTC.GOV  -----




--
To unsubscribe from fpu mailing list please visit http://www.opencores.org/mailinglists.shtml