[cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...

[OpenCores CVS Agent <cvs@www.lampret.com>]

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	02/12/26 15:00:41

Modified files:
	bench/verilog  : can_testbench.v 
	rtl/verilog    : can_registers.v can_top.v 
	sim/rtl_sim/run: wave.do 
Added files:
	bench/verilog  : can_testbench_defines.v 

Log message:
	Testbench define file added. Clock divider register added.

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