[cvs-checkins] pci/ ench/verilog/system.v tl/verilog/pci_brid ...

[OpenCores CVS Agent <cvs@www.lampret.com>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/10/08 16:17:07

Modified files:
	bench/verilog  : system.v 
	rtl/verilog    : pci_bridge32.v pci_target_unit.v pci_tpram.v 
	                 pciw_pcir_fifos.v top.v wb_slave_unit.v 
	                 wb_tpram.v wbw_wbr_fifos.v 
	sim/rtl_sim/bin: vs_file_list.lst 

Log message:
	Added BIST signals for RAMs.

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