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[cvs-checkins] i2c/bench/verilog wb_master_model.v tst_bench_ ...

CVSROOT:	/home/oc/cvs
Module name:	i2c
Changes by:	rherveille	02/03/17 11:26:47

Modified files:
	bench/verilog  : wb_master_model.v tst_bench_top.v 
	                 i2c_slave_model.v 

Log message:
	Fixed some race conditions in the i2c-slave model.
	Added debug information.
	Added headers.

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