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[cvs-checkins] ata/verilog/ocidec-1 ata.v controller.v counte ...

CVSROOT:	/home/oc/cvs
Module name:	ata
Changes by:	rherveille	01/07/09 20:48:44

Modified files:
	verilog/ocidec-1: ata.v controller.v counter.v pio_tctrl.v 

Log message:
	Added 'timescale to all files
	Fixed bug where control registers would always latch data, instead of when addressed

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