Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Tom Hawkins <tom1@launchbird.com>]

On Tuesday 27 May 2003 11:58 am, Shehryar Shaheen wrote:
> So what would Sytem Verilog have in the offing that
>  SystemC doesn't ?
>
> Would you think that the reason that SystemC is not popular is
>  cause the learning curve associated with a new language tends
>  to put off many users who already have a firm grip over current
>  HDLs ?

SystemC is not popular because C, object-orientation, and imperative 
programming are very poor languages and paradigms for describing 
hardware systems.

It is certainly not the learning curve.  In fact, most HW engineers 
are already masters of C, not to mention Perl, Python, Ruby, etc.

RTL designers live and breath dataflow, hierarchy, and component-based 
design methodologies -- this is part of the reason why HW engineers 
are better software developers than most software developers.

Unfortunately, SystemVerilog adds a lot of useless S/W baggage as 
well: classes, unions, a slew of C datatypes, forks/joins, 
semaphores, mailboxes.  Why did the SW guys controlling the standards 
committee feel the urge to add these features to Verilog?  Answer: 
Because 95% of all SW guys have never experienced anything outside 
C++ or Java -- arguably the 2 worse programming languages on the 
planet.   

But, of course, I'm biased. :-)  I only designed Confluence because 
choosing between Verilog and VHDL is picking a lesser of two evils,
and SystemC, Handel-C, et al, was a big step backwards.

-Tom

-- 
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
tom1@launchbird.com
http://www.launchbird.com/


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