RE: [oc] VHDL Process statement

["Radwin Zagala" <rzagala@softhome.net>]

Hi!

It will just get the previous value. In hardware, I think you'll have a
flip-flop with the D input tied to "Vcc", enable to "enable of
flip-flop", signal1 to "Q of flip-flop", txclk to "clk" and rst_n to
"reset".

Radwin

> -----Original Message-----
> From: owner-cores@opencores.org 
> [mailto:owner-cores@opencores.org] On Behalf Of twebel@gmx.de
> Sent: Wednesday, April 23, 2003 6:14 AM
> To: cores@opencores.org
> Subject: [oc] VHDL Process statement
> 
> 
> Hi,
> i read some vhdl code of the opencore HDLC and now i have
> a question regarding process stements and how the hardware looks like.
> 
> ..
> proc1: process (txclk, rst_n)
> variable state :STD_LOGIC
> 
> if rst_n = ´0´ then
>   state    := '0';
>   signal1 := '0';
>  elseif txclk'event and txclk = '1' then
>   if enable = '1' then
>       state    := '1';
>       signal1 := '1';
>   end if;
>  end if;
> end if;
> 
> What values have state, signal1  
> if the enable signal switches to '0' ?
> There is no elseif statement for that !!
> Thanks.
> 
> 
> 
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