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[oc] DCT Project [ROM64 and others]
Hello !
I have been trying to compile Cosine transform (DCT) [@
http://www.opencores.org/projects/dct/ ] with Max+plusII, i have found an error
on Database Builder from ROM64.vhd...
... the error says:
Error: Node':199886.IN2' missing source
(there are 768 errors like this one)
Probably it is my fault because i have not initialize ROM like i should or
something like that... but i can't find what the problem is.
I also would like to know...
1) What is ain(0) declared on div2_9_en.vhd, because it is never used.
(Code below)
2)On add12slow:
output_temp <= unsigned(a(11)&a) + unsigned(b(11)&b);
Why concatenate a(11)&a and b(11)&b ? It is that on the standard ?
----( Code )-------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY add12slow IS
PORT(
a : IN std_logic_vector (11 downto 0) ;
b : IN std_logic_vector (11 downto 0) ;
output : OUT std_logic_vector (12 downto 0)
);
-- Declarations
END add12slow ;
--
--
ARCHITECTURE beh OF add12slow IS
signal output_temp : unsigned(12 downto 0);
BEGIN
output_temp <= unsigned(a(11)&a) + unsigned(b(11)&b);
output <= std_logic_vector(output_temp);
END beh;
--------------------------------------------------------------------------------
Also, i would like to thank people that did this good work and want to share
it, so people like me can learn from them.
--
Cheers,
Héctor Orón
--(ROM64.vhd)--------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY ROM64 IS
PORT(
columns : IN std_logic_vector (2 downto 0) ;
compl : IN std_logic ;
enable_rom : IN std_logic ;
rows : IN std_logic_vector (2 downto 0) ;
output : OUT std_logic_vector (11 DOWNTO 0)
);
-- Declarations
END ROM64 ;
--
--
ARCHITECTURE beh OF ROM64 IS
-- ROM used for Forward Discrete Cosine Transform
type ROM_array is array (63 downto 0) of std_logic_vector(11 downto 0);
signal coeff_out : std_logic_vector(11 downto 0);
signal rt,ct : unsigned(2 downto 0);
--signal cmp_c1 : unsigned(11 downto 0);
signal cmp_c2 : std_logic_vector(11 downto 0);
--signal nottemp : std_logic_vector(7 downto 0);
signal coeff: ROM_array;
signal addr : integer range 0 to 63;
--signal ap : std_logic_vector(7 downto 0) := "01011011";
--signal bp : std_logic_vector(7 downto 0) := "01110110";
--signal cp : std_logic_vector(7 downto 0) := "00110001";
--signal dp : std_logic_vector(7 downto 0) := "01111110";
--signal ep : std_logic_vector(7 downto 0) := "01101010";
--signal fp : std_logic_vector(7 downto 0) := "01000111";
--signal gp : std_logic_vector(7 downto 0) := "00011001";
--signal am : std_logic_vector(7 downto 0) := "10100101";
--signal bm : std_logic_vector(7 downto 0) := "10001010";
--signal cm : std_logic_vector(7 downto 0) := "11001111";
--signal dm : std_logic_vector(7 downto 0) := "10000010";
--signal em : std_logic_vector(7 downto 0) := "10010110";
--signal fm : std_logic_vector(7 downto 0) := "10111001";
--signal gm : std_logic_vector(7 downto 0) := "11100111";
signal ap : std_logic_vector(11 downto 0) := "010110101000";
signal bp : std_logic_vector(11 downto 0) := "011101100100";
signal cp : std_logic_vector(11 downto 0) := "001100010000";
signal dp : std_logic_vector(11 downto 0) := "011111011001";
signal ep : std_logic_vector(11 downto 0) := "011010100111";
signal fp : std_logic_vector(11 downto 0) := "010001110010";
signal gp : std_logic_vector(11 downto 0) := "000110010000";
signal am : std_logic_vector(11 downto 0) := "101001011000";
signal bm : std_logic_vector(11 downto 0) := "100010011100";
signal cm : std_logic_vector(11 downto 0) := "110011110000";
signal dm : std_logic_vector(11 downto 0) := "100000100111";
signal em : std_logic_vector(11 downto 0) := "100101011001";
signal fm : std_logic_vector(11 downto 0) := "101110001110";
signal gm : std_logic_vector(11 downto 0) := "111001110000";
BEGIN
coeff(0) <= ap; -- A
coeff(1) <= ap; -- A
coeff(2) <= ap; -- A
coeff(3) <= ap; -- A
coeff(4) <= ap; -- A
coeff(5) <= ap; -- A
coeff(6) <= ap; -- A
coeff(7) <= ap; -- A
coeff(8) <= dp; -- D
coeff(9) <= ep; -- E
coeff(10) <= fp; -- F
coeff(11) <= gp; -- G
coeff(12) <= gm; -- -G
coeff(13) <= fm; -- -F
coeff(14) <= em; -- -E
coeff(15) <= dm; -- -D
coeff(16) <= bp; -- B
coeff(17) <= cp; -- C
coeff(18) <= cm; -- -C
coeff(19) <= bm; -- -B
coeff(20) <= bm; -- -B
coeff(21) <= cm; -- -C
coeff(22) <= cp; -- C
coeff(23) <= bp; -- B
coeff(24) <= ep; -- E
coeff(25) <= gm; -- -G
coeff(26) <= dm; -- -D
coeff(27) <= fm; -- -F
coeff(28) <= fp; -- F
coeff(29) <= dp; -- D
coeff(30) <= gp; -- G
coeff(31) <= em; -- -E
coeff(32) <= ap; -- A
coeff(33) <= am; -- -A
coeff(34) <= am; -- -A
coeff(35) <= ap; -- A
coeff(36) <= ap; -- A
coeff(37) <= am; -- -A
coeff(38) <= am; -- -A
coeff(39) <= ap; -- A
coeff(40) <= fp; -- F
coeff(41) <= dm; -- -D
coeff(42) <= gp; -- G
coeff(43) <= ep; -- E
coeff(44) <= em; -- -E
coeff(45) <= gm; -- -G
coeff(46) <= dp; -- D
coeff(47) <= fm; -- -F
coeff(48) <= cp; -- C
coeff(49) <= bm; -- -B
coeff(50) <= bp; -- B
coeff(51) <= cm; -- -C
coeff(52) <= cm; -- -C
coeff(53) <= bp; -- B
coeff(54) <= bm; -- -B
coeff(55) <= cp; -- C
coeff(56) <= gp; -- G
coeff(57) <= fm; -- -F
coeff(58) <= ep; -- E
coeff(59) <= dm; -- -D
coeff(60) <= dp; -- D
coeff(61) <= em; -- -E
coeff(62) <= fp; -- F
coeff(63) <= gm; -- -G
rt <= unsigned(rows);
ct <= unsigned(columns);
addr <= CONV_INTEGER(rt&ct);
with enable_rom select
coeff_out <= coeff(addr) when '1',
"000000000000" when others;
--nottemp <= not(coeff_out);
--cmp_c1 <= unsigned(nottemp) + "000000000001";
--cmp_c2 <= std_logic_vector(cmp_c1);
cmp_c2 <= not(coeff_out);
with compl select
output <= cmp_c2 when '1',
coeff_out when others;
END beh;
--(ROM64.vhd)-----------------------------------------[ END ]
--(div2_9_en.vhd)-----------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
ENTITY div2_9_en IS
PORT(
ain : IN std_logic_vector (12 downto 0) ;
enable : IN std_logic ;
aout : OUT std_logic_vector (11 downto 0)
);
-- Declarations
END div2_9_en ;
--
--
ARCHITECTURE struct OF div2_9_en IS
BEGIN
with enable select
aout <= ain(12 downto 1) when '1',
"000000000000" when others;
END struct;
--(div2_9_en.vhd)-----------------------------------------[ END ]
--
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