Re: [oc] Beyond Transmeta...

[Marko Mlinar <markom@opencores.org>]

Jim,

> In viewing this in terms of a RISC processor where an Add occures in 1
> cycle (and let's say the multiply occures in 1 cycle as well), the sample
> program takes 5 cycles (one for each statement). In the serial approach
> and assuming 32 bit words. And assuming that the bit array clocks
> at 32x the RISC, then the 32 bit RISC instructions take the equivilent
> of 32x5 clocks (160) whereas the availability of variables for computation
> begins at 3 cycles. Or, in excess of 50x the RISC processor.

> Conceptualization of this is one thing. Putting it into practice is
> another. To put this into practice the program "compiler" must determine an
> optimal configuration for routing the data and then "wire" the processor to
> perform the task. PLDs illustrate that a "processor" can be rewired
> however, the current design of the popular PLDs are designed for bussing
> data for parallel use.e.g. the result of an n-bit adder is available only
> after the complete result is available and not as the result propigates
> across width of the adder.

In practice, you would find it hard to make a multiplier that would fit your 
purpose, also your logic would switch many times, consuming more power than 
standard circuits, and not to speak of multi-phase clock issues.
But even when leaving aside the implementation issues, you have will problems 
with loops, function calls and sw model, especially with PLD idea.
There is also problem of debugging.

I had same/similar ideas with or2k, but when you try to put things in practice 
there are many (theorethical) problems. Thats why or2k is only 3x3 in size ;)

best regards,
Marko

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml