[oc] Questions in DMA IP Core ?

[NansonHuang@itri.org.tw]

 Hi, dear electronics elites,

 I have studied the DMA IP core spec. and organized some questions to
discuss with you used to use. In Fig. 2, there is a link between
Prioritizing Arbiter and DMA engine. What kind of information does it
convey ? Is it necessary ? In Fig. 10, it illustrates the so called " back
to back transfer ", how to explain it ?
In table 3 CSR register, it defines the PAUSE bit to pause DMA engine. If
once it paused, all channels are realted to and if the DMA relinquish the
bus. If it resume after that, how does DMA act ? DMA will continue the
un-completed transfer or re-start it. I am confused to the operation
situation. In table 6 Channel CSR Register,
there are 3 INT source Channel transferred CHK_SZ, Done and Error. Besides,
there are ERR and DONE bit as well. Could we combine them into one copy ?
They both indicate the status of DMA. At last, it defines the Channel
Address Mask Registers. I dont understand according to the explanation
listed in spec. Could you give me more information on it ?

 Thanks in advances and your time,

 Nanson


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