Re: [oc] Can I get the sdram controller by FPGA? (VHDL)

[myogananth@rediffmail.com.com]

whether any project availble in low power dissipiation viterbi decoder 
design using verilog







----- Original Message ----- 
From: joe_zhao@s...  
To: cores@o...  
Date: Tue, 26 Nov 2002 10:02:48 -0100 
Subject: Re: [oc] Can I get the sdram controller by FPGA? (VHDL) 

> 
> 
> I hope to get the sdram controller free core by FPGA (VHDL). 
> 
> Joe  zhao 
> 
> 11/26 
> ----- Original Message ----- 
> From: dheeraj_vij@r... 
> To: cores@o... 
> Date: Thu, 10 Oct 2002 11:43:51 -0100 
> Subject: Re: [oc] Can I get the 
> 
> > 
> > 
> > 
> > 
> > ----- Original Message ----- 
> > From: "=?gb2312?B?sNe35g==?=" <baifeng@m... > 
> > To: <cores@o... > 
> > Date: Tue, 5 Feb 2002 10:55:49 +0800 
> > Subject: Re: [oc] Can I get the "SDRAM controller VHDL" or 
> Verilog 
> > Source   Code? 
> > 
> > > 
> > > 
> > > hai servan, 
> > >       Can u send  me the  the source code of sdram 
> controller 
> > ? 
> > >        Thanks 
> > >       baifeng 
> > > 
> > > ----- Original Message ----- 
> > > From: "I. Servan Uzun" <isu@b... > 
> > > To: <cores@o... > 
> > > Sent: Saturday, February 02, 2002 7:53 PM 
> > > Subject: Re: [oc] Can I get the "SDRAM controller VHDL" 
> or 
> > Verilog 
> > > Source Code? 
> > > 
> > > 
> > > > Madhu, 
> > > > 
> > > > Below is the link for SDR SDRAM Controller Reference 
> > Design 
> > > > 
> > http://www.altera.com/products/ip/altera/m-alt-sdr-sdram.shtml 
> > > > 
> > > > I didn' t searched for the source code but it must 
> be 
> > > somewhere on 
> > > > the website. If you can not find it, I can send VHDL 
> > source 
> > > code to you 
> > > > by e-mail. 
> > > > 
> > > > Regards, 
> > > > - Servan 
> > > > 
> > > > ----- Original Message ----- 
> > > > From: "Madhusudhan Rao" <madhu_sudhana_rao@y... 
> > 
> > > > To: <cores@o... > 
> > > > Sent: Friday, February 01, 2002 11:23 PM 
> > > > Subject: Re: [oc] Can I get the "SDRAM controller 
> VHDL" 
> > or 
> > > Verilog Source 
> > > > Code? 
> > > > 
> > > > 
> > > > > hai servan, 
> > > > >      Can u give me the address link for the 
> source 
> > > > > code. 
> > > > > 
> > > > > Thanks 
> > > > > Madhu 
> > > > > 
> > > > > --- "I. Servan Uzun" <isu@b... > wrote: 
> > > > > > Altera has a SDRAM controller megacore 
> function 
> > with 
> > > > > > an application note. I 
> > > > > > have 
> > > > > > used it with APEX20KE device at 100MHz. 
> Source 
> > code 
> > > > > > of the core is also 
> > > > > > available  in VHDL 
> > > > > > on its website. 
> > > > > > 
> > > > > > - Servan 
> > > > > > 
> > > > > > ----- Original Message ----- 
> > > > > > From: "sphuynh" <sphuynh@m... > 
> > > > > > To: <cores@o... > 
> > > > > > Sent: Thursday, January 31, 2002 6:29 PM 
> > > > > > Subject: RE: [oc] Can I get the "SDRAM 
> > controller 
> > > > > > VHDL" or Verilog Source 
> > > > > > Code? 
> > > > > > 
> > > > > > 
> > > > > > > Xilinx have a couple application 
> notes and 
> > > source 
> > > > > > codes for SDRAM 
> > > > > > controller 
> > > > > > > for their Virtex and Spartan family.  
> I'm 
> > not 
> > > sure 
> > > > > > if this any useful to 
> > > > > > > you.  Below are the links. 
> > > > > > > 
> > > > > > > DDR SDRAM controller: 
> > > > > > > 
> http://www.xilinx.com/xapp/xapp200.pdf 
> > > > > > > 
> > > > > > > SDR SDRAM controller: 
> > > > > > > 
> http://www.xilinx.com/xapp/xapp134.pdf 
> > > > > > > 
> > > > > > > Son Huynh 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > -----Original Message----- 
> > > > > > > From: hanz@c... 
> > > > > > [mailto:hanz@c... ] 
> > > > > > > Sent: Tuesday, January 29, 2002 1:15 
> PM 
> > > > > > > To: cores@o... 
> > > > > > > Subject: [oc] Can I get the "SDRAM 
> > controller 
> > > > > > VHDL" or Verilog Source 
> > > > > > > Code? 
> > > > > > > 
> > > > > > > 
> > > > > > > I'm a master source student in KAIST. 
> > > > > > > 
> > > > > > > I've been designed CMOS Digital 
> camera 
> > system, 
> > > but 
> > > > > > I can't 
> > > > > > > 
> > > > > > > realize SDRAM controller using Altera 
> Flex 
> > > Chip. 
> > > > > > > 
> > > > > > > Can I get the "SDRAM controller VHDL" 
> or 
> > > Verilog 
> > > > > > Source Code? 
> > > > > > > 
> > > > > > > Thank you. 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > -- 
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> > > > > > 
> > > > > > 
> > > > > > 
> > > > > 
> > > > > 
> > > > > ===== 
> > > > > MadhusudhanaRao.M 
> > > > > 
> > > > > 
> > > > > 
> > > > 
> > > > 
> > > > 
> > > 
> > 
> 
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