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Re: [oc] New! FFT core
Welcome hanzy :)
This document is writen in two hours, so it was too simple,
give me some advice on what you are care about, I will write this part
first.
I write a fft sample with 1024 point 12 bit width, I put it at /cfft/imp
I try to fit it into Spartan2e100 -6,
The map result is:
Number of Slices: 807 out of 1,200 67%
Number of Slices containing
unrelated logic: 0 out of 807 0%
Number of Slice Flip Flops: 1,174 out of 2,400 48%
Total Number 4 input LUTs: 1,294 out of 2,400 53%
Number used as LUTs: 1,250
Number used as a route-thru: 43
Number used as Shift registers: 1
Number of bonded IOBs: 57 out of 142 40%
IOB Flip Flops: 1
Number of Block RAMs: 6 out of 10 60%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 1 out of 4 25%
Total equivalent gate count for design: 120,504
Additional JTAG gate count for IOBs: 2,784
The post timing result is:
Design statistics:
Minimum period: 10.580ns (Maximum frequency: 94.518MHz)
Minimum input arrival time before clock: 4.522ns
Minimum output required time after clock: 8.199ns
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
To: cores@o...
Date: Thu, 31 Oct 2002 16:32:19 +0700
Subject: Re: [oc] New! FFT core
>
>
> On Thursday 31 October 2002 15:27, hanzy wrote:
> > i just take a browse with your FFT core, i think your
> description is not
> > good, you can make more detailed description, and I will give
> you my
> > thoughts after careful read.
>
> Can you please also translate it to English ?
> Can you guys work together on this ?
>
> I can edit it as well, after you are done translating it.
> After me, may be John can can do a final round of editing ? ;*)
>
> rudi (ETL)
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