| Hi,      I intend to incorporate 
the Mini-Risc Core by Rudolf Usselmann with an FTDMA (similar to ByteFlight) 
controller. What I need to know is how to synthesize 
programs in the program memory (Xilinx Block RAM). The hex2v program 
generates a .rom file which is used within the test bench for 
simulations but for sysnthesis how to synthesize the program within the 
Block RAM or if there is a way to dynamically download 
programs in the Block RAM. I am using Xilinx WebPack 
and XC2S200 -5C Spartan-II  FPGA. In the $WebPackRoot/bin/nt directory there is 
a generatecore.exe utility. I rough guess I have that I would have to 
generate the Block RAM core with the program in it and then 
intantiate it in the Desisgn before synthesis. The generate core utility gives 
the following message C:\xilinx_webpack\bin\nt>generatecore Usage: generatecore [-cell <cellName>] [-component <componentName>] [-targetArch <targetDeviceFamily>] [-library 
<libraryName>] [-package <packageName>] [-outputFile <outputFileName>] [-outputDirectory <outputDirectory>] [-p {<ppair>}] [-a {<apair>}] <simName> But guessing and experimenting won't 
work (at least not fast enough). I'll be grateful if Rudolf Usselmann 
or any one else can  answer. Thanks in anticipation and kind 
regards Shehryar  |