[oc] conditional compilation in VHDL

[unni_cv@hotmail.com]

Hi,
    Is there any conditional compilation switches in VHDL, like the
`ifdef in verilog?  We can use generic and generate statemenst to
emulate `ifdef to an extend, but I think the flexibility is less.  I
wonder if there si any? I haven't come across yet?

unni
--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml