Re: [oc] Non-stalling pipeline?

[Ali Mashtizadeh <ali@alikat.org>]

Rudolf Usselmann wrote:
> 
> On Saturday 30 March 2002 01:10 am, you wrote:
> > http://www.sun.com/processors/UltraSPARC-III/specs.html
> >
> > Sun here says that their ultra sparc III has a 14 stage non stalling
> > pipeline. How is that possible or am i misunderstanding this?
> >
> > Ali
> 
> Well, the real question is WHY do pipelines have to be stalled
> in the first place ? I would like to suggest to view pipeline stalling
> as a design flaw in the first place. You stall a pipeline because
> you can not continue execution due to some dependency and
> or data not being available.
> 
> Sun finally sat down and "fixed" those problems. A properly
> engineered RISC should not need to stall it's pipeline.
> 
> regards,
> rudi
> 
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Well anyone have a sugestion on how it's done? I agree it's a flaw, but
how is it done when you have 14 stages that makes for many possible
dependencies and even with fowarding your bound to have one or two
unless either you reorder the instructions and place nop's when you need
to drop a clock cycle. But still with 14 stages and 4 way super scaler I
would think the reorder buffer needs to be greater than 4*14. And I do
not believe that sun is using out-of-order execution. If someone can
point me to some research papers/examples on this it would be nice.

Ali
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