Re: Re: [oc] PCI core - I can't synthesize.

["Jerzy Gbur" <furia1024@wp.pl>]

Hi!

> Just a suggestion - I believe you might be able to use the preprocessor
from
> Icarus verilog standalone. This might allow you to pre-process the design
> before feeding it to Xact.
>
> Steve Wilson
>
> On Wednesday 20 March 2002 09:43, you wrote:
> > Sorry,
> >
> > I meant the `else directive.
> >
> > Regardless, XST has many problems with verilog preprocessing. You will
> > notice problems with including files etc.

Thank You for all advices. For now I'd put double slash "//" before
problematic directives
and Syntesize and Implement passed OK. I'm saying for now becouse it's not
so actual problem.
Besides, thanks to all of You.
Maybe I'll try to rewrite the code to VHDL.....

Jurek

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