Re: [oc] VHDL or Verilog?

["Marko Mlinar" <markom@opencores.org>]

Hi!

There has been quite a lot of discussion/war on this subject.
Why don't you look at mailing list archives?

Marko

----- Original Message -----
From: <starz2far@juno.com>
To: <cores@opencores.org>
Sent: Monday, March 04, 2002 7:16 PM
Subject: [oc] VHDL or Verilog?


> Hello
>
> I am planning to take a course on intro to either VHDL or Verilog. Which
> is better? At the moment Im leaning towards Verilog, can you please tell
> me the difference and what should I take?
>
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